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INTRODUCTION

FAPESP and Intel invite interested researchers from public or private higher education or research institutions in the State of São Paulo to submit research proposals for funding under the cooperation agreement between FAPESP and Intel, and under the terms and conditions hereinafter set forth.

SUBJECT

Academic research on the novel approaches to employ Field Programmable Gate Arrays (FPGAs) in the context of security and cryptography, and the associated vertical domains.

OVERVIEW

Researchers in the State of São Paulo, Brazil, are invited to submit research proposals on FPGAs applied to security and cryptography, as well as to the overlaying vertical domain areas. FPGAs are expected to cause a major positive impact on the security of (sometimes overlapping) areas such as Automotive, Unmanned Aerial Vehicles (UAVs)/Drones, Artificial Intelligence (AI), Internet of Things (IoT), and Data Centers, just to cite a few. In some contexts, for example, FPGAs can provide cost-efficient flexibility to support security during the entire product lifecycle. In others scenarios, it can deliver novel ways of achieving higher reliability by adaptively optimizing redundancy, and even by serving as the foundation for deep learning. In addition, FPGAs can support the tailoring of algorithms to benefit areas on both sides of the spectrum, such as servers and IoT. In this CFP, Intel and FAPESP request research proposals leading to compelling techniques and technologies based on FPGAs that will help shape the future of security in areas of increasing relevance. It is worth emphasizing that the overarching goal is to provide an opportunity for researchers to explore and propose innovative ways to improve security by leveraging the benefits provided by FPGAs.

BACKGROUND

FPGAs have traditionally provided several benefits to systems design, such as flexibility, acceleration, ease of integration, fast prototyping, and shorter time-to-market (TTM). With the growing density in configurable elements and on-chip resources, FPGAs have been able to implement increasingly complex systems in a wide range of applications. Examples of domains that have traditionally benefited from FPGAs are Aerospace, Military, Telecommunications, Networking, and Embedded Systems. FPGAs have also been extensively used as the underlying platform to support research on algorithms improvements, hardware acceleration, HW/SW co-design.

Intel recently incorporated Altera, one of the two major players in the FPGA business. This acquisition opened many opportunities by applying FPGA technology to a wide variety of products. FPGAs have also been placed in central position in the company’s strategy for the virtuous cycle of growth. In addition to their traditional applications, FPGAs have been increasingly benefiting other areas such as Automotive, UAVs, AI, IoT, and Data Centers.

The aforementioned examples should not be taken as a limiting factor to the scope of the research proposal whatsoever. It cannot be overemphasized that the goal of taking advantage of this opportunity is to explore novel approaches and techniques based on FPGAs. However, it is important to notice that a great deal of academic and industrial research has been done on FPGA technology, and, as previously mentioned, FPGAs have been widely employed in several applications.

Research on a particular topic should address both comparisons with existing alternatives and variants to provide well-understood points of reference. Metrics of interest that may help support the efficiency, appropriateness, or feasibility of a given solution may include, but not be limited to:

• Implementation complexity. What is the required complexity of the implementation of a given solution, and how does that compare to other alternatives? What optimizations are possible that could reduce this complexity? Implementation complexity can be considered as area footprint, integration requirements, etc. How can a given solution be integrated in current systems?

• Performance. What kind of performance can be expected from the implementation of a given solution? How might that performance be improved through potential optimization approaches?

• Energy requirements. How much energy is required for the implementation of a specific solution? What components of the solution require the most energy? What are the possible optimizations to reduce energy requirements?

• Storage requirements. How much storage is required for the solution? How does this compare to various alternatives? What optimizations are possible?

• Side channel vulnerabilities and resistance . What side channel information vulnerabilities are associated with a specific solution? How does a given solution protect against side channels? What are the applicable techniques to address the problem of side channel attacks?

• Reconfigurability and adaptability. How flexible is the solution in terms of long-term upgrades and improvements? How does that improve security, or at least keep the same security level? What are the underlying security assumptions and how do they relate to actual applications? How does the solution evolve to support new usage contexts while keeping the same security level?

• Reliability and Safety. How does the solution increase the system reliability? What are the elements contributing to the system safety? What are the trade-offs? What is the solution’s resilience to faults? How can fault-tolerance be achieved efficiently?

Researchers are encouraged to make use of Intel platforms for their work, but there are no strict constraints beyond this broad guideline in order to allow flexibility of approach, device context, and usage scenario. For thoroughness, empirical analysis may also consider other relevant platforms as a point of comparison, for the broader ecosystem will be interested in a range of platforms.

RESEARCH AREAS

The focus of this research call, broadly stated, is on exploring the flexibility brought by FPGAs and its application in the security domain. Research proposals in response to this challenge are expected to address one or more of the following research vectors, in increasing order of priority: RV1: Cryptographic Research/Hardware Acceleration, RV2: Side Channel, RV3: AI and Security, RV4: Application Domains. Note that these vectors are not intended to be mutually exclusive. In addition, proposals that suggest a compelling topic lying outside these research vectors, yet in the spirit of program objectives and goals, are strongly encouraged . It should be noticed, however, that there has already been a considerable amount of previous research on FPGAs and their applications. Thus, it is expected that submissions cautiously and comprehensively analyze previous research in the selected focus area, and it is recommended that researchers provide compelling evidence to support the novelty of the research topic proposed.

RV1: Cryptographic Research/Hardware Acceleration. The goal of this research vector is to investigate innovative ways of benefiting from FPGAs as the underlying platform for cryptographic research as well as to provide hardware acceleration and efficient implementation in selected contexts. There has been growing importance of lightweight and post-quantum cryptographic algorithms followed by solid efforts in standardization processes, which makes them interesting candidates to be explored in the scope of this research. In addition to that, FPGAs can provide significant benefits in the context of performance-driven systems (such as in data centers), where, besides hardware acceleration, FPGAs can enable algorithms to dynamically adapt to workload changes. In the other end of the spectrum, lightweight strategies can benefit constrained devices such as in the IoT space. In this research vector, researchers are asked to investigate hardware implementation aspects of cryptographic algorithms based on an FPGA platform. Researchers are asked to identify key features and issues, to identify potential variants depending on the end application, and compare them against competing approaches. Evaluation metrics could be based on implementation complexity, performance gain, energy requirements, area footprint, storage requirements, and other key metrics.

RV2: Side-Channel. The goal of this research vector is to develop techniques to ensure that FPGA implementations of cryptographic algorithms and/or security mechanisms are not vulnerable to side-channel and fault attacks. Researchers are asked to identify key implementation strategies, both at the algorithm and design levels, by taking into account the FPGA features and internal architecture. Also in scope is the investigation whether constraints imposed by the FPGA fabric could lead to a particular side-channel properties that could be exploited. Besides side-channel, fault injection detection and mitigation are also in the scope of this research vector, which could, for example, explore concepts based on features such as reconfigurability and redundancy. Even though specific cryptographic algorithms and security mechanisms are not listed, this research vector could naturally consider lightweight and post-quantum algorithms as initial candidates. The results of the investigation could, for instance, specify what implementations have good and/or bad properties. The methodologies could also lead to recommendations to the academia and industry.

RV3: AI and Security. The goal of this research vector is to investigate the intersection between AI and security mechanisms by taking advantage of the performance and flexibility provided by FPGAs. AI could also provide benefits in adaptive optimization of cryptographic primitives, in which algorithms would dynamically learn the optimal configuration for a certain execution context. Similarly, AI could provide means to implement self-healing mechanisms aiming at higher reliability, and even improve resiliency against fault injection attacks. Deep learning could benefit intrusion detection by inferring anomalies at a higher level of abstraction, as well as launching an automatic system response. Control flow and data flow integrity is also in the scope of this research vector, where the reconfigurable platform would serve as an underlying mechanism to detect flows deviating from its expected behavior. Concepts with tightly coupled FPGAs to a processor could be explored. In this vector, researchers may consider exploring AI to devise efficient methods based on FPGAs to support security mechanisms.

RV4: Application Domains. The goal of this research vector is to investigate how application domains could benefit from the speed and flexibility of FPGAs. From another perspective, the selected application domains leverage several of the research vectors’ objectives presented above. Intel’s virtuous cycle of growth places FPGAs and memories in a central position fueling the whole cycle, which includes areas such as Automotive and UAVs. In all of these areas, security is a top priority to be fully addressed from the ground up. Automotive security, for instance, has gained increased importance, given recent car hacking incidents and the major impact that it can have to millions of people if security is not properly addressed. Researchers are invited to explore and leverage elements of the previous research vectors to enable significant advances in the aforementioned key strategic areas. Interesting FPGA-based security aspects to be evaluated may include (but are not limited to):

- What are efficient architectural strategies to provide security while ensuring safety in the automotive environment?

- How could reconfigurable elements efficiently enable self-healing and adaptability in security mechanisms?

- How could AI-based adaptive security mechanisms be applied for anomaly and intrusion detection?

- What are novel strategies that could lead to efficient reliability and fault tolerance approaches for security mechanisms while minimizing redundancy, which would be tailored to UAV and automotive contexts?

- How can FPGA fundamentally reshape the underlying in-vehicle networks and associated components (ECUs, gateways) to be able to control and manage vehicles, while guaranteeing security and functional safety?

- How to best leverage the flexibility provided by FPGAs to benefit in-vehicle electronics, in such a way that it can tolerate future architectures (bus, communication, etc), providing same and better features (including security), granted that they are now based on flexible hardware?

- In more general terms, how can traditional architectures/ infrastructures could benefit brought by FPGAs, and how can that be leveraged to devise novel security approaches?

Regardless of the research vector(s) addressed, the research should be well-grounded in real-world case studies and explore proof-of-concepts based on actual hardware platforms.

Goals of research This CFP suggests some areas of interest where FPGAs could provide significant enhancement in the state-of-the-art. It also asks researchers to explore and propose novel research vectors in which FPGAs would play a major role in security. 

In this context, FAPESP and INTEL seek projects that clearly address one or more of the broader research objectives:

• Propose novel approaches, architectures, and techniques that can significantly impact the security of domains such as automotive and UAVs;

• Devise approaches to leverage AI in the context of security, aiming at increased adaptability, anomaly detection, and self-healing;

• Identify techniques tailored to side-channel and fault-injection protection of cryptographic primitives implemented on FPGAs; and

• Characterize efficient implementations of lightweight and post-quantum cryptographic algorithms on FPGAs, as well as new strategies to leverage FPGAs in the context of hardware acceleration.

Depending on the research vector chosen or proposed, the research project should address a combination of the following specific goals:

Quantified Comparisons:

Goal 1: Researchers provide quantified comparisons between the solution variants and competing approaches. Metrics can include (but are not limited to):

• Complexity (e.g., number of operations)

• Area footprint (e.g. LEs)

• Performance (e.g. ops/sec, workload completion time)

• Energy requirements (e.g., performance/kJ or W)

• Code size (e.g., KB)

• Storage requirements (e.g., KB)

• Communication requirements (e.g. Mbps)

• Application-specific metrics

New Optimizations:

Goal 2: Researchers demonstrate that the solution provides significant improvement over state-of-the-art using one or more metrics defined in Goal 1.  

Side-Channel and Fault-Injection:

Goal 3a: Researchers demonstrate the side channel attack or fault injection feasibility and quantify its requirements and complexity.

Goal 3b: Researchers demonstrate the efficacy of a specific countermeasure and quantify the requirements and complexity.

ELIGIBILITY

In order to qualify for this Request for Proposals in the FAPESP-INTEL Agreement, the proposer should satisfy the following prerequisites:

a) The conditions and restrictions of the FAPESP Program for Cooperative Research for Technological Innovation (PITE) described at www.fapesp.br/pite are applied here, excluding those restrictions and conditions explicitly excepted in this CFP.

b) The proposals may be submitted by researchers from Higher Education or Research Institutions in the State of São Paulo.

c) Proposals that are incomplete, inaccurate, or are otherwise not responsive to the terms and conditions of this CFP will, at the sole discretion of the Joint Steering Committee for the FAPESP-INTEL cooperation, be excluded from consideration.

PROGRAM SCOPE AND FUNDING

FAPESP and INTEL contemplate funding a cluster of 2-year grant proposals. Each would be renewable annually contingent upon satisfactory progress and continued promise in research direction.

The total amount available for this CFP is US$ 200,000. FAPESP and INTEL reserve the right to propose lower funding levels for projects.

The appropriateness of the requested funding in relation to the proposal goals and qualification of the proposing team is a primary review consideration.

PROPOSAL FORMAT 

The proposal should clearly state the problems and opportunities to be addressed and the potential impact if the research is successful. It should specifically address the quantifiable goals listed in this request for proposals and provide milestones reflecting the progress towards them.

Each proposal must contain the items described at the SAGe System, according to the instructions of Annex I.

The list of documents that must be submitted is available at the SAGE System. The documents must be submitted in English, considering the following instructions.

FAPESP Curricular Summary , in English, for the PI, co-PI and each Associate Researcher. Instructions for elaborating the Curricular Summary are available at www.fapesp.br/en/6351.

Research Team : List of all contributing researchers, in English. For each one, his or her role in the research project must be defined succinctly, as well as the weekly workload. Each participant must agree with his or her participation in the project via the SAGE system.

Research Proposal s must be written in English and have 12 to 14 pages (not including bibliography and budget), containing the following sections.

1. Cover page {1 page} . Title of proposal, name(s) of author(s), contact information, name of university, funds requested, the amount of cost share (if any)

2. Executive summary {1 page} . Define the problem/challenge that this research will address, the effort’s technical objectives/success criteria, and the basic proposed approach.

3. Relevance and impact claims {1-2 pages }. This section is the centerpiece of the proposal. It should succinctly describe the uniqueness and non-incremental benefits of the proposed objective and approach relative to the state-of-the-art and current approaches.

4. Detailed technical rationale, approach, and constructive plan {2-4 pages} . Details of proposed research. Proposals should address key issues along one or more of the above research vectors (or another topic still addressing program objectives and goals), and the rationale should include a basis of confidence for meeting the program metrics.

5. Statement of work, schedule, milestones, success criteria and deliverables {2 pages} . Outline the scope of the effort including tasks to be performed, schedule, milestones, deliverables, and success criteria. It is understood that this is an exploratory research effort and schedules/deliverables reflect intentions rather than a firm commitment.

6. Proposal team {1-2 pages} . Summarize the members of the program team, their qualifications, and their level of participation in the project.

7. Other support {1 page} . List other contributions by the Host Institution to this project (cash, goods, or services), if any, but not including items such as the use of university facilities otherwise provided on an ongoing basis. Note that authors of selected proposals will be required to present an original letter on university letterhead signed by the director of the Host Institution certifying the commitment of any additional support.

8. Citations {unlimited}.

9. Requested budget description {unlimite d}. Proposals must include separate budget descriptions for the items requested to FAPESP (at the field R$/US$ at Sage) and to Intel (attached document). It is desirable to keep the fraction of the total amount requested for each of the parties at around 50%. Such a balance is desirable but not mandatory, and may deviate from 50% due to specific circumstances to be justified.

a) The budget items that may be requested to FAPESP are those traditionally supported by the Foundation and described in www.fapesp.br/1656.

b) The budget items that can be covered with funds from Intel should be limited to:

i. Resources invested in capital goods or equipment associated with the project if they are donated to the Higher Education and Research Institutions in the State of Sao Paulo;

ii. Resources invested in Scientific Initiation, Masters or Post-Doctoral fellowships with values at least equal to the grants from FAPESP for these fellowships;

iii. Resources invested in consumables and services of third parties when directly associated with the project;

iv. Resources invested in infrastructure associated with the project;

v. Resources for the temporary hiring, during the period of the project, of researchers and technical support staff dedicated to the project in the Host Institution.

vi. Resources for salary complementation of researchers participating in the project employed by the Host Institution;

vii. Special cases documented by a detailed justification within the proposal will be analyzed in each case by the Joint Steering Committee.

IMPORTANT: It is necessary to attach three quotes for each capital and equipment expense requested (national or imported), whose value exceeds ten minimum wages. If it is not possible to obtain the 3 quotes requested, please attach a clarification letter.

10. Fellowships {unlimited}: The proposed budget may include costs for fellowships. The ending dates for each fellowship must happen at or before the ending date of the project. Academic Fellowships can be covered with funds from Intel depending on the analysis of the proposal and the availability of resources, to be verified at the time of selection of proposals. For each requested fellowship a work plan with up to two pages must be submitted together with the research proposal. Work plans must include: Title for the Fellowship research project, Summary, and Description of the plan. It is not necessary to nominate the holder of the fellowship. If the grant is approved, the Principal Investigator will be in charge of organizing a public selection process to select the appointees for the fellowships through a merit review process. 

PROPOSAL SUBMISSION 

Proposals must be submitted via SAGE and will not be accepted by any other means.

No proposals will be accepted after the closing date for submission, nor will any addendum or explanation be accepted, unless those explicitly and formally requested by FAPESP or Intel.

EVALUATION CRITERIA 

All received proposals adherent to the terms of this Request for Proposals will be analyzed.

The selection process is based on merit review and comparative analysis. To this end FAPESP will use reviewers' reports and the Foundation’s Area and Supervising Panels.

The criteria used will be that applied to the selection of proposals in the FAPESP Program for Cooperative Research for Technological Innovation (PITE), with the addition of the analysis by the Joint Steering Committee for the FAPESP-INTEL cooperation.

Researchers participating in any submitted proposal will not take part in the analysis and selection process.

The evaluation criteria for this solicitation are as follows:

a) Adherence to the terms of this CFP;

b) Novelty and Ambition of the proposed academic research project, as it relates to the goals of this CFP;

c) Qualification of the research project, in the specification of clear goals, milestones, and success criteria. Clarity of challenges to be overcome and the scientific, technical and material means and ways for this, in relation to the state-of-the-art in the Field, including interface definitions, testing methodology, and plans for experimental deployment;

d) Adequate existing institutional infrastructure, offered by the Hosting Institution;

e) Qualifications of Principal Investigator and his team, including previous history of work in areas relevant to this CFP, successful completion of previously funded projects, teaching awards, and publications, all of those items being demonstrated in the Curricular Summary of the CV of the Principal Investigators;

f) Ability to complete the project, including the adequacy of available resources, institutional support, reasonableness of timelines, and number and qualifications of identified contributors. Encompasses the efficient use of requested resources and funding, and represent realistic results for the value invested;

g) Potential for wide dissemination and use of intellectual property created, including specific plans for publications, conference presentations, web sites, as well as plans to distribute content in multiple formats or languages;

h) Formation of new researchers and professionals, as a result of the execution of the Project;

i) Potential for technological innovation. The extent to which the proposal’s problem formulation and key approaches are innovative, important, and relevant to the problem at hand. Novelty and ambition of the proposed academic research project, as it relates to the goals of this CFP. Potential for technological innovation as measured by comparisons with existing and competing technologies.

j) Potential contribution and relevance to INTEL. The estimated degree to which proposals have a substantial potential for influencing the direction of INTEL’s long range technology plans.

SCHEDULE

Event	Date
Launching of the CFP at FAPESP Web site	July 24, 2017
Last date for receiving proposals	October 11,2017
Publication of results of the analysis and selection process	February 9,2018

ANNOUNCEMENT OF RESULTS 

The results of the selection process will be announced in FAPESP’s Web Site at www.fapesp.br and by direct communication to the proponents.

CONTRACTING OF THE SELECTED PROPOSALS 

For each research proposal selected, the relationship between FAPESP, INTEL and the Principal Investigator Institution will be determined by an agreement defining:

a. Schedule of disbursements and financial reporting on the amounts disbursed;

b. Definition and timing of expected results at each stage of the project;

c. Intellectual property, confidentiality and possible exploitation of project results;

d. Term;

e. Legal venue.

CANCELLATION OF THE AWARD 

The award may be cancelled by Intel and FAPESP by mutual agreement, in the event of justifiable cause, on the basis of evaluation by the Scientific Directors of FAPESP and Intel. Cancellation does not preclude other measures that might be deemed necessary.

GRANTS, PROGRESS ANALYSIS AND EVALUATION 

If the application is approved, a Grant Contract will be made, which will be signed by the Principal Investigator and the Host Institution´s representative.

The results will be evaluated by progress reports and financial reports that should be submitted on the dates established in the Grant Contract.

AGREEMENT TO TERMS AND CONDITIONS 

By submitting an application under this CFP, applicants confirm that they have read, understood and agreed to the terms and conditions of the CFP and the conditions attached to any successful awards.

INFORMATION AND CLARIFICATION

All questions related to this CFP must be directed to: Chamada_intel@fapesp.br.

Please, put “CFP FAPESP-INTEL” in the subject line of your e-mail to ensure a prompt and proper response.

 

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Annex I: Specific Instructions for SAGe System (Guidelines for SAGe submission)

1. Principle Investigator must be registered in the SAGe system:

(I) Researchers who do not have a SAGe registration should initially do so by accessing the SAGe page at www.fapesp.br/sage, clicking on “Sem cadastro?” and fill in the requested data. It is not enough to just register as a user, it is necessary to complete the cadastral data;

(II) Researchers from the State of São Paulo, already registered, must log in to SAGe with the usual identification and password to access the system homepage.

2. On the home page, select from the menu options "Acesso rápido – Atividades do Pesquisador", the link “ Nova Proposta Inicial”;

3. In the Current Calls section, select and click the link for this Call for proposals.

4. The system will display the menu "Incluir proposta" on the following page to confirm the selected Call.

5. Click the “Incluir” button to start preparing your proposal.

6. Include the requested data in all the tabs, including the list of documents to be attached;

7. Attention to the obligation to fill all items marked with "*". You must submit the project at the end of the form. Saved project does not mean submitted project;

8. If you have any doubts, you can use the Manuals link on the SAGe home page and, in the Manuals page, search for explanations in the Manuais de Apoio aos Pesquisadores.

9. IMPORTANT: It is strongly recommended to periodically check the pending proposals using the "Validar" option. This can be repeatedly as the proposal is built, allowing the necessary arrangements for submission to be made in time. When selecting the option " Validar", the SAGe system will present the impediments pending to submit the proposal considering the items that were already inserted. In case of doubts about the use of SAGE system, in addition to the Manuals, FAPESP also provides assistance at the Information Sector (11 3838-4000).

Attention: Since 01/11/2016, for proposal submission, it is mandatory to attach a scanned copy of the identification document to the SAGe register. (Access menu "Meus dados> Alteração de Cadastro" and attach the requested document in the "Documento de Identificação" in the section “ Identificação”). This obligation applies to all beneficiaries and PI’s of fellowships and grants.

 

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